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p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core 2 kb/4 kb/8 kb 3 v low-power flash with 256-byte data ram rev. 08 15 december 2004 product data 1. general description the p89lpc920/921/922/9221 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. the p89lpc920/921/922/9221 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80c51 devices. many system-level functions have been incorporated into the p89lpc920/921/922/9221 in order to reduce component count, board space, and system cost. 2. features 2.1 principal features n 2 kb/4 kb/8 kb flash code memory with 1 kb erasable sectors, 64-byte erasable page size, and single byte erase. n 256-byte ram data memory. n two 16-bit counter/timers. each timer may be con?gured to toggle a port output upon timer over?ow or to become a pwm output. n real-time clock that can also be used as a system timer. n two analog comparators with selectable inputs and reference source. n enhanced uart with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities. n 400 khz byte-wide i 2 c-bus communication port. n con?gurable on-chip oscillator with frequency range and rc oscillator options (selected by user programmed flash con?guration bits). the rc oscillator (factory calibrated to 1 %) option allows operation without external oscillator components. oscillator options support frequencies from 20 khz to the maximum operating frequency of 18 mhz. the rc oscillator option is selectable and ?ne tunable. n 2.4 v to 3.6 v v dd operating range. i/o pins are 5 v tolerant (may be pulled up or driven to 5.5 v). n high drive current (20 ma) on eight i/o pins on the p89lpc9221 (p0.3 to p0.7, p1.4, p1.6, p1.7).
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 2 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2.2 additional features n 15 i/o pins minimum. up to 18 i/o pins while using on-chip oscillator and reset options. n 20-pin tssop and dip packages. n a high performance 80c51 cpu provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 mhz. this is six times the performance of the standard 80c51 running at the same clock frequency. a lower clock frequency for the same performance results in power savings and reduced emi. n in-application programming of the flash code memory. this allows changing the code in a running application. n serial flash programming allows simple in-circuit production coding. flash security bits prevent reading of sensitive application programs. n watchdog timer with separate on-chip oscillator, requiring no external components. the watchdog prescaler is selectable from eight values. n low voltage reset (brownout detect) allows a graceful system shutdown when power fails. may optionally be con?gured as an interrupt. n idle and two different power-down reduced power modes. improved wake-up from power-down mode (a low interrupt input starts execution). typical power-down current is 1 m a (total power-down with voltage comparators disabled). n active-low reset. on-chip power-on reset allows operation without external reset components. a reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. a software reset function is also available. n oscillator fail detect. the watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. n programmable port output con?guration options: u quasi-bidirectional, u open drain, u push-pull, u input-only. n port input pattern match detect. port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. n led drive capability (20 ma) on all port pins. a maximum limit is speci?ed for the entire chip (160 ma for the p89lpc9221; 80 ma for the p89lpc920/921/922). n controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. n only power and ground connections are required to operate the p89lpc920/921/922/9221 when internal reset option is selected. n four interrupt priority levels. n eight keypad interrupt inputs, plus two additional external interrupt inputs. n second data pointer. n schmitt trigger port inputs. n emulation support.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 3 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 3. ordering information 3.1 ordering options table 1: ordering information type number package name description version p89lpc920fdh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 p89lpc921fdh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 P89LPC922FDH tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 p89lpc922fn dip20 plastic dual in-line package; 20 leads (300 mil) sot146-1 p89lpc9221fn dip20 plastic dual in-line package; 20 leads (300 mil) sot146-1 p89lpc9221fdh tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 table 2: part options type number flash memory temperature range frequency p89lpc920fdh 2 kb - 40 c to +85 c 0 mhz to 18 mhz p89lpc921fdh 4 kb - 40 c to +85 c 0 mhz to 18 mhz P89LPC922FDH 8 kb - 40 c to +85 c 0 mhz to 18 mhz p89lpc922fn 8 kb - 40 c to +85 c 0 mhz to 18 mhz p89lpc9221fn 8 kb - 40 c to +85 c 0 mhz to 18 mhz p89lpc9221fdh 8 kb - 40 c to +85 c 0 mhz to 18 mhz
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 4 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. block diagram fig 1. block diagram. high performance accelerated 2-clock 80c51 cpu 2 kb/4 kb/8 kb code flash 256-byte data ram port 3 configurable i/os port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock configurable oscillator on-chip rc oscillator internal bus crystal or resonator power monitor (power-on reset, brownout reset) 002aaa410 uart real-time clock/ system timer i 2 c timer 0 timer 1 watchdog timer and oscillator analog comparators p89lpc920/921/922/9221
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 5 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. pinning information 5.1 pinning fig 2. tssop20 pin con?guration. fig 3. dip20 pin con?guration. handbook, halfpage p89lpc920fdh p89lpc921fdh P89LPC922FDH p89lpc9221fdh 002aaa408 1 2 3 4 5 6 7 8 9 10 kbi0/cmp2/p0.0 p1.7 p1.6 rst/p1.5 v ss xtal1/p3.1 clkout/xtal2/p3.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 p0.1/cin2b/kbi1 p0.2/cin2a/kbi2 p0.3/cin1b/kbi3 p0.4/cin1a/kbi4 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 p1.0/txd p1.1/rxd 20 19 18 17 16 15 14 13 12 11 handbook, halfpage p89lpc922fn p89lpc9221fn 002aaa407 1 2 3 4 5 6 7 8 9 10 kbi0/cmp2/p0.0 p1.7 p1.6 rst/p1.5 v ss xtal1/p3.1 clkout/xtal2/p3.0 int1/p1.4 sda/int0/p1.3 scl/t0/p1.2 p0.1/cin2b/kbi1 p0.2/cin2a/kbi2 p0.3/cin1b/kbi3 p0.4/cin1a/kbi4 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 p1.0/txd p1.1/rxd 20 19 18 17 16 15 14 13 12 11
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 6 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5.2 pin description table 3: pin description symbol pin type description p0.0 to p0.7 i/o port 0: port 0 is an 8-bit i/o port with a user-con?gurable output type. during reset port 0 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 0 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 8.12.1 port con?gurations and table 8 dc electrical characteristics for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt triggered inputs. port 0 also provides various special functions as described below: 1 i/o p0.0 port 0 bit 0. o cmp2 comparator 2 output. i kbi0 keyboard input 0. 20 i/o p0.1 port 0 bit 1. i cin2b comparator 2 positive input b. i kbi1 keyboard input 1. 19 i/o p0.2 port 0 bit 2. i cin2a comparator 2 positive input a. i kbi2 keyboard input 2. 18 i/o p0.3 port 0 bit 3. high current source (p89lpc9221). i cin1b comparator 1 positive input b. i kbi3 keyboard input 3. 17 i/o p0.4 port 0 bit 4. high current source (p89lpc9221). i cin1a comparator 1 positive input a. i kbi4 keyboard input 4. 16 i/o p0.5 port 0 bit 5. high current source (p89lpc9221). i cmpref comparator reference (negative) input. i kbi5 keyboard input 5. 14 i/o p0.6 port 0 bit 6. high current source (p89lpc9221). o cmp1 comparator 1 output. i kbi6 keyboard input 6. 13 i/o p0.7 port 0 bit 7. high current source (p89lpc9221). i/o t1 timer/counter 1 external count input or over?ow output. i kbi7 keyboard input 7.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 7 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. p1.0 to p1.7 i/o, i [1] port 1: port 1 is an 8-bit i/o port with a user-con?gurable output type, except for three pins as noted below. during reset port 1 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of the con?gurable port 1 pins as inputs and outputs depends upon the port con?guration selected. each of the con?gurable port pins are programmed independently. refer to section 8.12.1 port con?gurations and table 8 dc electrical characteristics for details. p1.2 - p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt triggered inputs. port 1 also provides various special functions as described below: 12 i/o p1.0 port 1 bit 0. o txd transmitter output for the serial port. 11 i/o p1.1 port 1 bit 1. i rxd receiver input for the serial port. 10 i/o p1.2 port 1 bit 2 (open-drain when used as output). i/o t0 timer/counter 0 external count input or over?ow output (open-drain when used as output). i/o scl i 2 c serial clock input/output. 9 i/o p1.3 port 1 bit 3 (open-drain when used as output). i int0 external interrupt 0 input. i/o sda i 2 c serial data input/output. 8 i/o p1.4 port 1 bit 4. high current source (p89lpc9221). i int1 external interrupt 1 input. 4i p1.5 port 1 bit 5 (input only). i rst external reset input (if selected via flash con?guration). a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execution at address 0. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. 3 i/o p1.6 port 1 bit 6. high current source (p89lpc9221). 2 i/o p1.7 port 1 bit 7. high current source (p89lpc9221). table 3: pin description continued symbol pin type description
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 8 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] input/output for p1.0-p1.4, p1.6, p1.7. input for p1.5. 6. logic symbol p3.0 to p3.1 i/o port 3: port 3 is an 2-bit i/o port with a user-con?gurable output type. during reset port 3 latches are con?gured in the input only mode with the internal pull-up disabled. the operation of port 3 pins as inputs and outputs depends upon the port con?guration selected. each port pin is con?gured independently. refer to section 8.12.1 port con?gurations and table 8 dc electrical characteristics for details. all pins have schmitt triggered inputs. port 3 also provides various special functions as described below: 7 i/o p3.0 port 3 bit 0. o xtal2 output from the oscillator ampli?er (when a crystal oscillator option is selected via the flash con?guration. o clkout cpu clock divided by 2 when enabled via sfr bit (enclk - trim.6). it can be used if the cpu clock is the internal rc oscillator, watchdog oscillator or external clock input, except when xtal1/xtal2 are used to generate clock source for the real time clock/system timer. 6 i/o p3.1 port 3 bit 1. i xtal1 input to the oscillator circuit and internal clock generator circuits (when selected via the flash con?guration). it can be a port pin if internal rc oscillator or watchdog oscillator is used as the cpu clock source, and if xtal1/xtal2 are not used to generate the clock for the real time clock/system timer. v ss 5i ground: 0 v reference. v dd 15 i power supply: this is the power supply voltage for normal operation as well as idle and power down modes. table 3: pin description continued symbol pin type description fig 4. logic symbol. v dd v ss p89lpc920/921/922/9221 port 0 port 3 port 1 txd rxd t0 int0 int1 rst scl sda 002aaa409 cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 t1 xtal2 xtal1 kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 kbi6 kbi7 clkout
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 9 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. special function registers remark: special function registers (sfrs) accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0 or 1 can only be written and read as follows: C - unless otherwise speci?ed, must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 08 15 december 2004 10 of 46 table 4: special function registers * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit address e7 e6 e5 e4 e3 e2 e1 e0 acc* accumulator e0h 00 00000000 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 [1] 000000x0 bit address f7 f6 f5 f4 f3 f2 f1 f0 b* b register f0h 00 00000000 brgr0 [2] baud rate generator rate low beh 00 00000000 brgr1 [2] baud rate generator rate high bfh 00 00000000 brgcon baud rate generator control bdh - - - - - - sbrgs brgen 00 xxxxxx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00 [1] xx000000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx000000 divm cpu clock divide-by-m control 95h 00 00000000 dptr data pointer (2 bytes) dph data pointer high 83h 00 00000000 dpl data pointer low 82h 00 00000000 fmadrh program flash address high e7h 00 00000000 fmadrl program flash address low e6h 00 00000000 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 01110000 program flash control (write) e4h fmcmd. 7 fmcmd. 6 fmcmd. 5 fmcmd. 4 fmcmd. 3 fmcmd. 2 fmcmd. 1 fmcmd. 0 fmdata program flash data e5h 00 00000000 i2adr i 2 c slave address register dbh i2adr.6 i2adr.5 i2adr.4 i2adr.3 i2adr.2 i2adr.1 i2adr.0 gc 00 00000000 bit address df de dd dc db da d9 d8 i2con* i 2 c control register d8h - i2en sta sto si aa - crsel 00 x00000x0 i2dat i 2 c data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 00000000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 08 15 december 2004 11 of 46 i2scll serial clock generator/scl duty cycle register low dch 00 00000000 i2stat i 2 c status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 11111000 bit address af ae ad ac ab aa a9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 [1] 00000000 bit address ef ee ed ec eb ea e9 e8 ien1* interrupt enable 1 e8h - est - - - ec ekbi ei2c 00 [1] 00x00000 bit address bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [1] x0000000 ip0h interrupt priority 0 high b7h - pwdrt h pboh psh/ psrh pt1h px1h pt0h px0h 00 [1] x0000000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h - pst - - - pc pkbi pi2c 00 [1] 00x00000 ip1h interrupt priority 1 high f7h - psth - - - pch pkbih pi2ch 00 [1] 00x00000 kbcon keypad control register 94h - - - - - - patn _sel kbif 00 [1] xxxxxx00 kbmask keypad interrupt mask register 86h 00 00000000 kbpatn keypad pattern register 93h ff 11111111 bit address 87 86 85 84 83 82 81 80 p0* port 0 80h t1/kb7 cmp1 /kb6 cmpref /kb5 cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 cmp2 /kb0 [1] bit address 97 96 95 94 93 92 91 90 p1* port 1 90h - - rst int1 int0/ sda t0/scl rxd txd [1] bit address b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h - - - - - - xtal1 xtal2 [1] p0m1 port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1.5) (p0m1.4) (p0m1.3) (p0m1.2) (p0m1.1) (p0m1.0) ff 11111111 p0m2 port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2.5) (p0m2.4) (p0m2.3) (p0m2.2) (p0m2.1) (p0m2.0) 00 00000000 p1m1 port 1 output mode 1 91h (p1m1.7) (p1m1.6) - (p1m1.4) (p1m1.3) (p1m1.2) (p1m1.1) (p1m1.0) d3 [1] 11x1xx11 table 4: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 08 15 december 2004 12 of 46 p1m2 port 1 output mode 2 92h (p1m2.7) (p1m2.6) - (p1m2.4) (p1m2.3) (p1m2.2) (p1m2.1) (p1m2.0) 00 [1] 00x0xx00 p3m1 port 3 output mode 1 b1h - - - - - - (p3m1.1) (p3m1.0) 03 [1] xxxxxx11 p3m2 port 3 output mode 2 b2h - - - - - - (p3m2.1) (p3m2.0) 00 [1] xxxxxx00 pcon power control register 87h smod1 smod0 bopd boi gf1 gf0 pmod1 pmod0 00 00000000 pcona power control register a b5h rtcpd - vcpd - i2pd - spd - 00 [1] 00000000 bit address d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h 00000000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00h xx00000x rstsrc reset source register dfh - - bof pof r_bk r_wd r_sf r_ex [3] rtccon real-time clock control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [1][6] rtch real-time clock register high d2h 00 [6] 00000000 rtcl real-time clock register low d3h 00 [6] 00000000 saddr serial port address register a9h 00 00000000 saden serial port address enable b9h 00 00000000 sbuf serial port data buffer register 99h xx xxxxxxxx bit address 9f 9e 9d 9c 9b 9a 99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 00000000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 00000000 sp stack pointer 81h 07 00000111 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0xxx0 bit address 8f 8e 8d 8c 8b 8a 89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 00000000 th0 timer 0 high 8ch 00 00000000 th1 timer 1 high 8dh 00 00000000 tl0 timer 0 low 8ah 00 00000000 tl1 timer 1 low 8bh 00 00000000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 00000000 table 4: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 08 15 december 2004 13 of 46 [1] all ports are in input only (high impedance) state after power-up. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is 0. if any are written while brgen = 1, the result is unpredic table. [3] the rstsrc register re?ects the cause of the p89lpc920/921/922/9221 reset. upon a power-up reset, all reset source ?ags are cleared except pof and bof; the power-on reset value is xx110000. [4] after reset, the value is 111001x1, i.e., pre2-pre0 are all 1, wdrun = 1 and wdclk = 1. wdtof bit is 1 after watchdog reset and is 0 after power-on reset. other resets will not affect wdtof. [5] on power-on reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initializatio n of the trim register. [6] the only reset source that affects these sfrs is power-on reset. trim internal oscillator trim register 96h - enclk trim.5 trim.4 trim.3 trim.2 trim.1 trim.0 [5] [6] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [4] [6] wdl watchdog load c1h ff 11111111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 4: special function registers continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 14 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. functional description remark: please refer to the p89lpc920/921/922/9221 users manual for a more detailed functional description. 8.1 enhanced cpu the p89lpc920/921/922/9221 uses an enhanced 80c51 cpu which runs at 6 times the speed of standard 80c51 devices. a machine cycle consists of two cpu clock cycles, and most instructions execute in one or two machine cycles. 8.2 clocks 8.2.1 clock de?nitions the p89lpc920/921/922/9221 device has several internal clocks as de?ned below: oscclk input to the divm clock divider. oscclk is selected from one of four clock sources (see figure 5 ) and can also be optionally divided to a slower frequency (see section 8.7 cpu clock (cclk) modi?cation: divm register ). note: f osc is de?ned as the oscclk frequency. cclk cpu clock; output of the clock divider. there are two cclk cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four cclk cycles). rcclk the internal 7.373 mhz rc oscillator output. pclk clock for the various peripheral devices and is cclk/2 8.2.2 cpu clock (oscclk) the p89lpc920/921/922/9221 provides several user-selectable oscillator options in generating the cpu clock. this allows optimization for a range of needs from high precision to lowest possible cost. these options are con?gured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip rc oscillator, an oscillator using an external crystal, or an external clock source. the crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 khz to 12 mhz. 8.2.3 low speed oscillator option this option supports an external crystal in the range of 20 khz to 100 khz. ceramic resonators are also supported in this con?guration. 8.2.4 medium speed oscillator option this option supports an external crystal in the range of 100 khz to 4 mhz. ceramic resonators are also supported in this con?guration. 8.2.5 high speed oscillator option this option supports an external crystal in the range of 4 mhz to 18 mhz. ceramic resonators are also supported in this con?guration. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 15 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. 8.2.6 clock output the p89lpc920/921/922/9221 supports a user-selectable clock output function on the xtal2/clkout pin when crystal oscillator is not being used. this condition occurs if another clock source has been selected (on-chip rc oscillator, watchdog oscillator, external clock input on x1) and if the real-time clock is not using the crystal oscillator as its clock source. this allows external devices to synchronize to the p89lpc920/921/922/9221. this output is enabled by the enclk bit in the trim register. the frequency of this clock output is 1 2 that of the cclk. if the clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. 8.3 on-chip rc oscillator option the p89lpc920/921/922/9221 has a 6-bit trim register that can be used to tune the frequency of the rc oscillator. during reset, the trim value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 mhz, 1% at room temperature. end-user applications can write to the trim register to adjust the on-chip rc oscillator to other frequencies. 8.4 watchdog oscillator option the watchdog has a separate oscillator which has a frequency of 400 khz. this oscillator can be used to save power when a high clock frequency is not needed. 8.5 external clock input option in this con?guration, the processor clock is derived from an external source driving the xtal1/p3.1 pin. the rate may be from 0 hz up to 12 mhz. the xtal2/p3.0 pin may be used as a standard port pin or a clock output. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 16 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 5. block diagram of oscillator control. ? 2 002aaa424 rtc cpu wdt baud rate generator divm cclk uart oscclk i 2 c pclk timer 0 and timer 1 high freq. med. freq. low freq. xtal1 xtal2 rc oscillator watchdog oscillator (7.3728 mhz) (400 khz)
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 17 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.6 cpu clock (cclk) wake-up delay the p89lpc920/921/922/9221 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. if the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 oscclk cycles plus 60 to 100 m s. if the clock source is either the internal rc oscillator, watchdog oscillator, or external clock, the delay is 224 oscclk cycles plus 60 to 100 m s. 8.7 cpu clock (cclk) modi?cation: divm register the oscclk frequency can be divided down up to 510 times by con?guring a dividing register, divm, to generate cclk. this feature makes it possible to temporarily run the cpu at a lower rate, reducing power consumption. by dividing the clock, the cpu can retain the ability to respond to events that would not exit idle mode by executing its normal program at a lower rate. this can also allow bypassing the oscillator start-up time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time without interrupting code execution. 8.8 low power select the p89lpc920/921/922/9221 is designed to run at 18 mhz (cclk) maximum. however, if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to 1 to lower the power consumption further. on any reset, clklp is 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower. 8.9 memory organization the various p89lpc920/921/922/9221 memory spaces are as follows: ? data 128 bytes of internal data memory space (00h:7fh) accessed via direct or indirect addressing, using instruction other than movx and movc. all or part of the stack may be in this area. ? i data indirect data. 256 bytes of internal data memory space (00h:ffh) accessed via indirect addressing using instructions other than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 bytes immediately above it. ? sfr special function registers. selected cpu registers and peripheral control and status registers, accessible only via direct addressing. ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the p89lpc920/921/922/9221 has 2 kb/4 kb/8 kb of on-chip code memory.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 18 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.10 data ram arrangement the 256 bytes of on-chip ram are organized as shown in ta b l e 5 . 8.11 interrupts the p89lpc920/921/922/9221 uses a four priority level interrupt structure. this allows great ?exibility in controlling the handling of the many interrupt sources. the p89lpc920/921/922/9221 supports 12 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port tx, serial port rx, combined serial port rx/tx, brownout detect, watchdog/real-time clock, i 2 c, keyboard, and comparators 1 and 2. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts. each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers ip0, ip0h, ip1, and ip1h. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. if two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. if requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve pending requests of the same priority level. 8.11.1 external interrupt inputs the p89lpc920/921/922/9221 has two external interrupt inputs as well as the keypad interrupt function. the two interrupt inputs are identical to those present on the standard 80c51 microcontrollers. these external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit it1 or it0 in register tcon. in edge-triggered mode if successive samples of the intn pin show a high in one cycle and a low in the next cycle, the interrupt request ?ag ien in tcon is set, causing an interrupt request. if an external interrupt is enabled when the p89lpc920/921/922/9221 is put into power-down or idle mode, the interrupt will cause the processor to wake-up and resume operation. refer to section 8.14 power reduction modes for details. table 5: on-chip data memory usages type data ram size (bytes) data memory that can be addressed directly and indirectly 128 idata memory that can be addressed indirectly 256
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 19 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.12 i/o ports the p89lpc920/921/922/9221 has three i/o ports: port 0, port 1, and port 3. ports 0 and 1 are 8-bit ports, and port 3 is a 2-bit port. the exact number of i/o pins available depend upon the clock and reset options chosen, as shown in ta b l e 6 . [1] required for operation above 12 mhz. 8.12.1 port con?gurations all but three i/o port pins on the p89lpc920/921/922/9221 may be con?gured by software to one of four types on a bit-by-bit basis. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and input-only. two con?guration registers for each port select the output type for each port pin. p1.5 ( rst) can only be an input and cannot be con?gured. fig 6. interrupt sources, interrupt enables, and power-down wake-up sources. 002aaa418 ie0 ex0 ie1 ex1 bof ebo kbif ekbi interrupt to cpu wake-up (if in power-down) ewdrt cmf2 cmf1 ec ea (ie0.7) tf0 et0 tf1 et1 ti & ri/ri es/esr ti est si ei2c rtcf ertc (rtccon.1) wdovf table 6: number of i/o pins available clock source reset option number of i/o pins (20-pin package) on-chip oscillator or watchdog oscillator no external reset (except during power-up) 18 external rst pin supported [1] 17 external clock input no external reset (except during power-up) 17 external rst pin supported [1] 16 low/medium/high speed oscillator (external crystal or resonator) no external reset (except during power-up) 16 external rst pin supported [1] 15
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 20 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. p1.2 (scl/t0) and p1.3 (sda/ int0) may only be con?gured to be either input-only or open-drain. 8.12.2 quasi-bidirectional output con?guration quasi-bidirectional output type can be used as both an input and output without the need to recon?gure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is driven low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. the p89lpc920/921/922/9221 is a 3 v device, but the pins are 5 v-tolerant. in quasi-bidirectional mode, if a user applies 5 v on the pin, there will be a current ?owing from the pin to v dd , causing extra power consumption. therefore, applying 5 v in quasi-bidirectional mode is discouraged. a quasi-bidirectional port pin has a schmitt-triggered input that also has a glitch suppression circuit. 8.12.3 open-drain output con?guration the open-drain output con?guration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. to be used as a logic output, a port con?gured in this manner must have an external pull-up, typically a resistor tied to v dd . an open-drain port pin has a schmitt-triggered input that also has a glitch suppression circuit. 8.12.4 input-only con?guration the input-only port con?guration has no output drivers. it is a schmitt-triggered input that also has a glitch suppression circuit. 8.12.5 push-pull output con?guration the push-pull output con?guration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. a push-pull port pin has a schmitt-triggered input that also has a glitch suppression circuit. the p89lpc9221 device has high source current on eight pins in push-pull mode. see table 8 dc electrical characteristics . 8.12.6 port 0 analog functions the p89lpc920/921/922/9221 incorporates two analog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. digital outputs are disabled by putting the port output into the input-only (high impedance) mode as described in section 8.12.4 . digital inputs on port 0 may be disabled through the use of the pt0ad register, bits 1:5. on any reset, pt0ad1:5 defaults to 0s to enable digital functions.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 21 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.12.7 additional port features after power-up, all pins are in input-only mode. please note that this is different from the lpc76x series of devices. ? after power-up, all i/o pins except p1.5, may be con?gured by software. ? pin p1.5 is input only. pins p1.2 and p1.3 and are con?gurable for either input-only or open-drain. every output on the p89lpc920/921/922/9221 has been designed to sink typical led drive current. however, there is a maximum total output current for all ports which must not be exceeded. please refer to table 8 dc electrical characteristics for detailed speci?cations. all ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. the slew rate is factory-set to approximately 10 ns rise and fall times. 8.13 power monitoring functions the p89lpc920/921/922/9221 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect. 8.13.1 brownout detection the brownout detect function determines if the power supply voltage drops below a certain level. the default operation is for a brownout detection to cause a processor reset, however it may alternatively be con?gured to generate an interrupt. brownout detection may be enabled or disabled in software. if brownout detection is enabled, the brownout condition occurs when v dd falls below the brownout trip voltage, v bo (see table 8 dc electrical characteristics ), and is negated when v dd rises above v bo . if the p89lpc920/921/922/9221 device is to operate with a power supply that can be below 2.7 v, boe should be left in the unprogrammed state so that the device can operate at 2.4 v, otherwise continuous brownout reset may prevent the device from operating. for correct activation of brownout detect, the v dd rise and fall times must be observed. please see table 8 dc electrical characteristics for speci?cations. 8.13.2 power-on detection the power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. the pof ?ag in the rstsrc register is set to indicate an initial power-up condition. the pof ?ag will remain set until cleared by software. 8.14 power reduction modes the p89lpc920/921/922/9221 supports three different power reduction modes. these modes are idle mode, power-down mode, and total power-down mode.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 22 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.14.1 idle mode idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled interrupt source or reset may terminate idle mode. 8.14.2 power-down mode the power-down mode stops the oscillator in order to minimize power consumption. the p89lpc920/921/922/9221 exits power-down mode via any reset, or certain interrupts. in power-down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram contents at the point where power-down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ram , therefore it is highly recommended to wake up the processor via reset in this case. v dd must be raised to within the operating range before the power-down mode is exited. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include: brownout detect, watchdog timer, comparators (note that comparators can be powered-down separately), and real-time clock (rtc)/system timer. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. 8.14.3 total power-down mode this is the same as power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. the internal rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled. if the internal rc oscillator is used to clock the rtc during power-down, there will be high power consumption. please use an external low frequency clock to achieve low power with the real-time clock running during power-down. 8.15 reset the p1.5/ rst pin can function as either an active-low reset input or as a digital input, p1.5. the rpe (reset pin enable) bit in ucfg1, when set to 1, enables the external reset input function on p1.5. when cleared, p1.5 may be used as an input pin. remark: during a power-up sequence, the rpe selection is overridden and this pin will always function as a reset input. an external circuit connected to this pin should not hold this pin low during a power-on sequence as this will keep the device in reset. after power-up this input will function either as an external reset input or as a digital input as de?ned by the rpe bit. only a power-up reset will temporarily override the selection de?ned by rpe bit. other sources of reset will not override the rpe bit. remark: during a power cycle, v dd must fall below v por (see table 8 dc electrical characteristics on page 36 ) before power is reapplied, in order to ensure a power-on reset. reset can be triggered from the following sources:
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 23 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? external reset pin (during power-up or if user con?gured via ucfg1). this option must be used for an oscillator frequency above 12 mhz); ? power-on detect; ? brownout detect; ? watchdog timer; ? software reset; ? uart break character detect reset. for every reset source, there is a ?ag in the reset register, rstsrc. the user can read this register to determine the most recent reset source. these ?ag bits can be cleared in software by writing a 0 to the corresponding bit. more than one ?ag bit may be set: ? during a power-on reset, both pof and bof are set but the other ?ag bits are cleared. ? for any other reset, previously set ?ag bits that have not been cleared will remain set. 8.15.1 reset vector following reset, the p89lpc920/921/922/9221 will fetch instructions from either address 0000h or the boot address. the boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00h. the boot address will be used if a uart break reset occurs, or the non-volatile boot status bit (boots tat.0) = 1, or the device is forced into isp mode during power-on (see p89lpc920/921/922/9221 users manual ). otherwise, instructions will be fetched from address 0000h. 8.16 timers/counters 0 and 1 the p89lpc920/921/922/9221 has two general purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. both can be con?gured to operate either as timers or event counter. an option to automatically toggle the t0 and/or t1 pins upon timer over?ow has been added. in the timer function, the register is incremented every machine cycle. in the counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once during every machine cycle. timer 0 and timer 1 have ?ve operating modes (modes 0, 1, 2, 3 and 6). modes 0, 1, 2 and 6 are the same for both timers/counters. mode 3 is different. 8.16.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. in this mode, the timer register is con?gured as a 13-bit register. mode 0 operation is the same for timer 0 and timer 1. 8.16.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register are used.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 24 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.16.3 mode 2 mode 2 con?gures the timer register as an 8-bit counter with automatic reload. mode 2 operation is the same for timer 0 and timer 1. 8.16.4 mode 3 when timer 1 is in mode 3 it is stopped. timer 0 in mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. when timer 1 is in mode 3 it can still be used by the serial port as a baud rate generator. 8.16.5 mode 6 in this mode, the corresponding timer can be changed to a pwm with a full period of 256 timer clocks. 8.16.6 timer over?ow toggle output timers 0 and 1 can be con?gured to automatically toggle a port output whenever a timer over?ow occurs. the same device pins that are used for the t0 and t1 count inputs are also used for the timer toggle outputs. the port outputs will be a logic 1 prior to the ?rst timer over?ow when this mode is turned on. 8.17 real-time clock/system timer the p89lpc920/921/922/9221 has a simple real-time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. the real-time clock can be a wake-up or an interrupt source. the real-time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. when it reaches all 0s, the counter will be reloaded again and the rtcf ?ag will be set. the clock source for this counter can be either the cpu clock (cclk) or the xtal oscillator, provided that the xtal oscillator is not being used as the cpu clock. if the xtal oscillator is used as the cpu clock, then the rtc will use cclk as its clock source. only power-on reset will reset the real-time clock and its associated sfrs to the default state. 8.18 uart the p89lpc920/921/922/9221 has an enhanced uart that is compatible with the conventional 80c51 uart except that timer 2 over?ow cannot be used as a baud rate source. the p89lpc920/921/922/9221 does include an independent baud rate generator. the baud rate can be selected from the oscillator (divided by a constant), timer 1 over?ow, or the independent baud rate generator. in addition to the baud rate generation, enhancements over the standard 80c51 uart include framing error detection, automatic address recognition, selectable double buffering and several interrupt options.the uart can be operated in 4 modes: shift register, 8-bit uart, 9-bit uart, and cpu clock/32 or cpu clock/16. 8.18.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb ?rst. the baud rate is ?xed at 1 16 of the cpu clock frequency.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 25 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.18.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), and a stop bit (logical 1). when data is received, the stop bit is stored in rb8 in special function register scon. the baud rate is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section 8.18.5 baud rate generator and selection ). 8.18.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logical 1). when data is transmitted, the 9 th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9 th data bit goes into rb8 in special function register scon, while the stop bit is not saved. the baud rate is programmable to either 1 16 or 1 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 8.18.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logical 0), 8 data bits (lsb ?rst), a programmable 9 th data bit, and a stop bit (logical 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 over?ow rate or the baud rate generator (described in section 8.18.5 baud rate generator and selection ). 8.18.5 baud rate generator and selection the p89lpc920/921/922/9221 enhanced uart has an independent baud rate generator. the baud rate is determined by a baud-rate preprogrammed into the brgr1 and brgr0 sfrs which together form a 16-bit baud rate divisor value that works in a similar manner as timer 1 but is much more accurate. if the baud rate generator is used, timer 1 can be used for other timing functions. the uart can use either timer 1 or the baud rate generator output (see figure 7 ). note that timer t1 is further divided by 2 if the smod1 bit (pcon.7) is set. the independent baud rate generator uses oscclk. 8.18.6 framing error framing error is reported in the status register (sstat). in addition, if smod0 (pcon.6) is 1, framing errors can be made available in scon.7 respectively. if smod0 is 0, scon.7 is sm0. it is recommended that sm0 and sm1 (scon.7:6) are set up when smod0 is 0. fig 7. baud rate sources for uart (modes 1, 3). baud rate modes 1 and 3 sbrgs = 1 sbrgs = 0 smod1 = 0 smod1 = 1 ? 2 timer 1 overflow (pclk-based) baud rate generator (cclk-based) 002aaa419
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 26 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.18.7 break detect break detect is reported in the status register (sstat). a break is detected when 11 consecutive bits are sensed low. the break detect can be used to reset the device and force the device into isp mode. 8.18.8 double buffering the uart has a transmit double buffer that allows buffering of the next character to be written to sbuf while the ?rst character is being transmitted. double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. double buffering can be disabled. if disabled (dbmod, i.e., ss tat. 7 = 0), the uart is compatible with the conventional 80c51 uart. if enabled, the uart allows writing to snbuf while the previous data is being shifted out. double buffering is only allowed in modes 1, 2 and 3. when operated in mode 0, double buffering must be disabled (dbmod = 0). 8.18.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) unlike the conventional uart, in double buffering mode, the tx interrupt is generated when the double buffer is ready to receive new data. 8.18.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) if double buffering is disabled tb8 can be written before or after sbuf is written, as long as tb8 is updated some time before that bit is shifted out. tb8 must not be changed until the bit is shifted out, as indicated by the tx interrupt. if double buffering is enabled, tb8 must be updated before sbuf is written, as tb8 will be double-buffered together with sbuf data.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 27 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.19 i 2 c-bus serial interface i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bidirectional data transfer between masters and slaves ? multimaster bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus con?guration is shown in figure 8 . the p89lpc920/921/922/9221 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz. fig 8. i 2 c-bus con?guration. other device with i 2 c-bus interface sda scl r p r p other device with i 2 c-bus interface p1.3/sda p1.2/scl p89lpc920/921/922 i 2 c-bus 002aaa420
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 28 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 9. i 2 c-bus serial interface block diagram. internal bus 002aaa421 address register comparator shift register 8 i2adr ack bit counter / arbitration & sync logic 8 i2dat timing & control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1.3 p1.3/sda p1.2/scl p1.2 timer 1 overflow control registers & scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 29 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.20 analog comparators two analog comparators are provided on the p89lpc920/921/922/9221. input and output options allow use of the comparators in a number of different con?gurations. comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be con?gured to cause an interrupt when the output value changes. the overall connections to both comparators are shown in figure 10 . the comparators function to v dd = 2.4 v. when each comparator is ?rst enabled, the comparator output and interrupt ?ag are not guaranteed to be stable for 10 microseconds. the corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ?ag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. when a comparator is disabled the comparators output, cox, goes high. if the comparator output was low and then is disabled, the resulting transition of the comparator output from a low to high state will set the comparator ?ag, cmfx. this will cause an interrupt if the comparator interrupt is enabled. the user should therefore disable the comparator interrupt prior to disabling the comparator. additionally, the user should clear the comparator ?ag, cmfx, after disabling the comparator. 8.20.1 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as v ref , is 1.23 v 10%. fig 10. comparator input and output connections. comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref oe1 change detect co1 cmf1 interrupt 002aaa422 cmp1 (p0.6) ec change detect cmf2 comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 30 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.20.2 comparator interrupt each comparator has an interrupt ?ag contained in its con?guration register. this ?ag is set whenever the comparator output changes state. the ?ag may be polled by software or may be used to generate an interrupt. the two comparators use one common interrupt vector. if both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ?ags to determine which comparator caused the interrupt. 8.20.3 comparators and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated, but both comparators are disabled automatically in total power-down mode. if a comparator interrupt is enabled (except in total power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. if the comparator output to a pin is enabled, the pin should be con?gured in the push-pull mode in order to obtain fast switching times while in power-down mode. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact should be taken into account when system power consumption is an issue. to minimize power consumption, the user can disable the comparators via pcona.5, or put the device in total power-down mode. 8.21 keypad interrupt (kbi) the keypad interrupt function is intended primarily to allow a single interrupt to be generated when port 0 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. the user can con?gure the port via sfrs for different tasks. the keypad interrupt mask register (kbmask) is used to de?ne which input pins connected to port 0 can trigger the interrupt. the keypad pattern register (kbpatn) is used to de?ne a pattern that is compared to the value of port 0. the keypad interrupt flag (kbif) in the keypad interrupt control register (kbcon) is set when the condition is matched while the keypad interrupt function is active. an interrupt will be generated if enabled. the patn_sel bit in the keypad interrupt control register (kbcon) is used to de?ne equal or not-equal for the comparison. in order to use the keypad interrupt as an original kbi function like in 87lpc76x series, the user needs to set kbpatn = 0ffh and patn_sel = 1 (not equal), then any key connected to port 0 which is enabled by the kbmask register will cause the hardware to set kbif and generate an interrupt if it has been enabled. the interrupt may be used to wake up the cpu from idle or power-down modes. this feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. in order to set the ?ag and cause an interrupt, the pattern on port 0 must be held longer than 6 cclks.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 31 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.22 watchdog timer the watchdog timer causes a system reset when it under?ows as a result of a failure to feed the timer prior to the timer reaching its terminal count. it consists of a programmable 12-bit prescaler, and an 8-bit down counter. the down counter is decremented by a tap taken from the prescaler. the clock source for the prescaler is either the pclk or the nominal 400 khz watchdog oscillator. the watchdog timer can only be reset by a power-on reset. when the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. figure 11 shows the watchdog timer in watchdog mode. feeding the watchdog requires a two-byte sequence. if pclk is selected as the watchdog clock and the cpu is powered-down, the watchdog is disabled. the watchdog timer has a time-out period that ranges from a few m s to a few seconds. please refer to the p89lpc920/921/922/9221 users manual for more details. 8.23 additional features 8.23.1 software reset the srst bit in auxr1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. care should be taken when writing to auxr1 to avoid accidental software resets. 8.23.2 dual data pointers the dual data pointers (dptr) provides two different data pointers to specify the address used with certain instructions. the dps bit in the auxr1 register selects one of the two data pointers. bit 2 of auxr1 is permanently wired as a logic 0 so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibility of inadvertently altering other bits in the register. (1) watchdog reset can also be caused by an invalid feed sequence, or by writing to wdcon not immediately followed by a feed sequence. fig 11. watchdog timer in watchdog mode (wdte = 1). pre2 pre1 pre0 C C wdrun wdtof wdclk wdcon (a7h) control register prescaler 002aaa423 shadow register for wdcon 8-bit down counter wdl (c1h) watchdog oscillator pclk ? 32 mov wfeed1, #0a5h mov wfeed2, #05ah reset see note (1)
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 32 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8.24 flash program memory 8.24.1 general description the p89lpc920/921/922/9221 flash memory provides in-circuit electrical erasure and programming. the flash can be read, erased, or written as bytes. the sector and page erase functions can erase any flash sector (1 kb) or page (64 bytes). the chip erase operation will erase the entire program memory. in-system programming and standard parallel programming are both available. on-chip erase and write timing generation contribute to a user-friendly programming interface. the p89lpc920/921/922/9221 flash reliably stores memory contents even after 10,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. the p89lpc920/921/922/9221 uses v dd as the supply voltage to perform the program/erase algorithms. 8.24.2 features ? parallel programming with industry-standard commercial programmers. ? in-circuit serial programming (icp) with industry-standard commercial programmers. ? iap-lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application. ? internal ?xed boot rom, containing low-level in-application programming (iap) routines that can be called from the end application (in addition to iap-lite). ? default serial loader providing in-system programming (isp) via the serial port, located in upper end of user program memory. ? boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing ?exibility to the user. ? programming and erase over the full operating voltage range. ? read/programming/erase using isp/iap/iap-lite. ? any ?ash program or erase operation in 2 ms. ? programmable security for the code in the flash for each sector. ? >100,000 typical erase/program cycles for each byte. ? 10 year minimum data retention. 8.24.3 isp and iap capabilities of the p89lpc920/921/922/9221 flash organization: the p89lpc920/921/922/9221 program memory consists of two/four/eight 1 kb sectors. each sector can be further divided into 64-byte pages. in addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. an in-application programming (iap) interface is provided to allow the end users application to erase and reprogram the user code memory. in addition, erasing and reprogramming of user-programmable bytes including ucfg1, the boot status bit and the boot vector are supported. as shipped from the factory, the upper 512 bytes of user code space contains a serial in-system programming (isp) routine allowing for the device to be programmed in circuit through the serial port.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 33 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. flash programming and erasing: there are three methods of erasing or programming of the flash memory that may be used. first, the flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point. second, the on-chip isp boot loader may be invoked. this isp boot loader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application. third, the flash may be programmed or erased using the parallel method by using a commercially available eprom programmer which supports this device. this device does not provide for direct veri?cation of code memory contents. instead this device provides a 32-bit crc result on either a sector or the entire 2 kb/4 kb/8 kb of user code space. boot rom: when the microcontroller programs its own flash memory, all of the low-level details are handled by code that is contained in a boot rom that is separate from the flash memory. a user program simply calls the common entry point in the boot rom with appropriate parameters to accomplish the desired operation. the boot rom include operations such as erase sector, erase page, program page, crc, program security bit, etc. the boot rom occupies the program memory space at the top of the address space from ff00h to feffh, thereby not con?icting with the user program memory space. power-on reset code execution: the p89lpc920/921/922/9221 contains two special flash elements: the boot vector and the boot status bit. following reset, the p89lpc920/921/922/9221 examines the contents of the boot status bit. if the boot status bit is set to zero, power-up execution starts at location 0000h, which is the normal start address of the users application code. when the boot status bit is set to a one, the contents of the boot vector is used as the high byte of the execution address and the low byte is set to 00h. the factory default setting is 1fh for the p89lpc9221 and p89lpc922, and corresponds to the address 1f00h for the default isp boot loader. the factory default setting is 0fh for the p89lpc921 and corresponds to the address 0f00h for the default isp boot loader. the factory default setting for the lpc920 is 07h and corresponds to the address 0700h. this boot loader is pre-programmed at the factory into this address space and can be erased by the user. users who wish to use this loader should take precautions to avoid erasing the 1 kb sector from 1c00h to 1fffh in the p89lpc922/9221 or the 1 kb sector from 0c00h to 0fffh in the p89lpc921, or the 1 kb sector from 0400h to 07ffh in the p89lpc920. instead, the page erase function can be used to erase the eight 64-byte pages which comprise the lower 512 bytes of the sector. a custom boot loader can be written with the boot vector set to the custom boot loader, if desired. hardware activation of the boot loader: the boot loader can also be executed by forcing the device into isp mode during a power-on sequence (see the p89lpc920/921/922/9221 users manual for speci?c information). this has the same effect as having a non-zero boot status bit. this allows an application to be built that will normally execute user code but can be manually forced into isp operation. if the factory default setting for the boot vector is changed, it will no longer point to the factory pre-programmed isp boot loader code. if this happens, the only way it is possible to change the contents of the boot vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the boot vector
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 34 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. and boot status bit. after programming the flash, the boot status bit should be programmed to zero in order to allow execution of the users application code beginning at address 0000h. in-system programming (isp): in-system programming is performed without removing the microcontroller from the system. the in-system programming facility consists of a series of internal hardware resources coupled with internal ?rmware to facilitate remote programming of the p89lpc920/921/922/9221 through the serial port. this ?rmware is provided by philips and embedded within each p89lpc920/921/922/9221 device. the philips in-system programming facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the isp function uses ?ve pins (v dd , v ss , txd, rxd, and rst). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. please see the p89lpc920/921/922/9221 users manual for additional details. in-application programming (iap): several in-application programming (iap) calls are available for use by an application program to permit selective erasing and programming of flash sectors, pages, security bits, con?guration bytes, and device identi?cation. all calls are made through a common interface, pgm_mtp. the programming functions are selected by setting up the microcontrollers registers before making a call to pgm_mtp at ff00h. please see the p89lpc920/921/922/9221 users manual for additional details. in-circuit programming (icp): in-circuit programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system. the in-circuit programming facility consists of a series of internal hardware resources to facilitate remote programming of the p89lpc920/921/922/9221 through a two-wire serial interface. philips has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. the icp function uses ?ve pins (v dd , v ss , p0.5, p0.4, and rst). only a small connector needs to be available to interface your application to an external programmer in order to use this feature. 8.25 user con?guration bytes a number of user-con?gurable features of the p89lpc920/921/922/9221 must be de?ned at power-up and therefore cannot be set by the program after start of execution. these features are con?gured through the use of the flash byte ucfg1. please see the p89lpc920/921/922/9221 users manual for additional details. 8.26 user sector security bytes there are two/four/eight user sector security bytes, each corresponding to one sector. please see the p89lpc920/921/922/9221 users manual for additional details.
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 35 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. limiting values [1] the following applies to limiting values: a) stresses above those listed under ta bl e 7 may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in table 8 dc electrical characteristics , table 9 ac characteristics and table 10 ac characteristics of this speci?cation are not implied. b) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. c) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. table 7: limiting values [1] in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit t amb(bias) operating bias ambient temperature - 55 +125 c t stg storage temperature range - 65 +150 c v xtal voltage on xtal1, xtal2 pin to v ss -v dd + 0.5 v v n voltage on any other pin to v ss - 0.5 +5.5 v i oh(i/o) high-level output current per i/o pin, p89lpc9221 p0.3 to p0.7, p1.4, p1.6, p1.7 -20ma all other i/o pins - 8 ma high-level output current per i/o pin, p89lpc920/921/922 -8ma i ol(i/o) low-level output current per i/o pin - 20 ma i i/o(tot)(max) maximum total i/o current, p89lpc9221 - 160 ma maximum total i/o current, p89lpc920/921/922 -80ma p tot(pack) total power dissipation per package based on package heat transfer, not device power consumption - 1.5 w
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 36 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. static characteristics table 8: dc electrical characteristics v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit i dd(oper) power supply current, operating 3.6 v; 12 mhz [2] - 9 15 ma 3.6 v; 18 mhz [2] - 11.5 20 ma i dd(idle) power supply current, idle mode 3.6 v; 12 mhz [2] - 3.25 5 ma 3.6 v; 18 mhz [2] -57ma i dd(pd) power supply current, power-down mode, voltage comparators powered-down 3.6 v [2] -5580 m a i dd(tpd) power supply current, total power-down mode 3.6 v [2] -15 m a (dv dd /dt) r v dd rise rate - - 2 mv/ m s (dv dd /dt) f v dd fall rate - - 50 mv/ m s v por power-on reset detect voltage - - 0.2 v v ram ram keep-alive voltage 1.5 - - v v th(hl) negative-going threshold voltage except scl, sda 0.22v dd 0.4v dd -v v il low-level input voltage scl, sda only - 0.5 - 0.3v dd v v th(lh) positive-going threshold voltage except scl, sda - 0.6v dd 0.7v dd v v ih high-level input voltage scl, sda only 0.7v dd - 5.5 v v hys hysteresis voltage port 1 - 0.2v dd -v v ol low-level output voltage; all ports, all modes except hi-z [3] i ol = 20 ma - 0.6 1.0 v i ol = 3.2 ma - 0.2 0.3 v v oh high-level output voltage i oh = - 20 ma; push-pull mode p0.3 to p0.7, p1.4, p1.6, p1.7 0.8v dd --v i oh = - 3.2 ma; push-pull mode, all other ports v dd - 0.7 v dd - 0.4 - v i oh = - 20 m a; quasi-bidirectional mode, all ports v dd - 0.3 v dd - 0.2 - v c ig input/output pin capacitance [4] - - 15 pf i il logical 0 input current, all ports v in = 0.4 v [5] -- - 80 m a i li input leakage current, all ports v in =v il or v ih [6] -- 10 m a i tl logical 1-to-0 transition current, all ports v in = 2.0 v at v dd = 3.6 v [7] , [8] - 30 - - 450 m a r rst internal reset pull-up resistor 10 - 30 k w
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 37 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] typical ratings are not guaranteed. the values listed are at room temperature, 3 v. [2] the i dd(oper) ,i dd(idle) , and i dd(pd) speci?cations are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer. [3] see table 7 limiting values [1] on page 35 for steady state (non-transient) limits on i ol or i oh . if i ol /i oh exceeds the test condition, v ol /v oh may exceed the related speci?cation. [4] pin capacitance is characterized but not tested. [5] measured with port in quasi-bidirectional mode. [6] measured with port in high-impedance mode. [7] ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups). does not apply to open-drain p ins. [8] port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. this curr ent is highest when v in is approximately 2 v. v bo brownout trip voltage with bov = 0, bopd = 1 2.4 v < v dd < 3.6 v 2.40 - 2.70 v v ref bandgap reference voltage 1.11 1.23 1.34 v tc (vref) bandgap temperature coef?cient - 10 20 ppm/ c table 8: dc electrical characteristics continued v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 38 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. dynamic characteristics [1] parameters are valid over operating temperature range unless otherwise speci?ed. parts are tested to 2 mhz, but are guarantee d to operate down to 0 hz. table 9: ac characteristics v dd = 2.4 v to 3.6 v unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =12mhz unit min max min max f rcosc internal rc oscillator frequency (nominal f = 7.3728 mhz) trimmed to 1% at t amb =25 c 7.189 7.557 7.189 7.557 mhz f wdosc internal watchdog oscillator frequency (nominal f = 400 khz) 320 520 320 520 khz f osc oscillator frequency 0 12 - - mhz t clcl clock cycle see figure 13 83 - - - ns f clkp clklp active frequency 0 8 - - mhz glitch ?lter glitch rejection, p1.5/ rst pin - 50 - 50 ns signal acceptance, p1.5/ rst pin 125 - 125 - ns glitch rejection, any pin except p1.5/ rst - 15 - 15 ns signal acceptance, any pin except p1.5/ rst 50 - 50 - ns external clock t chcx high time see figure 13 33 t clcl - t clcx 33 - ns t clcx low time see figure 13 33 t clcl - t chcx 33 - ns t clch rise time see figure 13 -8 -8ns t chcl fall time see figure 13 -8 -8ns shift register (uart mode 0) t xlxl serial port clock cycle time 16 t clcl - 1333 - ns t qvxh output data set-up to clock rising edge 13 t clcl - 1083 - ns t xhqx output data hold after clock rising edge -t clcl + 20 - 103 ns t xhdx input data hold after clock rising edge - 0 - 0 ns t dvxh input data valid to clock rising edge 150 - 150 - ns
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 39 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] parameters are valid over operating temperature range unless otherwise speci?ed. parts are tested to 2 mhz, but are guarantee d to operate down to 0 hz. [2] when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is req uired to hold the device in reset at power-up until v dd has reached its speci?ed level. when system power is removed v dd will fall below the minimum speci?ed operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum speci?ed operating voltage. table 10: ac characteristics v dd = 3.0 v to 3.6 v unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, unless otherwise speci?ed. [1] symbol parameter conditions variable clock f osc =18mhz unit min max min max f rcosc internal rc oscillator frequency (nominal f = 7.3728 mhz) trimmed to 1% at t amb =25 c 7.189 7.557 7.189 7.557 mhz f wdosc internal watchdog oscillator frequency (nominal f = 400 khz) 320 520 320 520 khz f osc oscillator frequency [2] 0 18 - - mhz t clcl clock cycle see figure 13 55 - - - ns f clkp clklp active frequency 0 8 - - mhz glitch ?lter glitch rejection, p1.5/ rst pin - 50 - 50 ns signal acceptance, p1.5/ rst pin 125 - 125 - ns glitch rejection, any pin except p1.5/ rst - 15 - 15 ns signal acceptance, any pin except p1.5/ rst 50 - 50 - ns external clock t chcx high time see figure 13 22 t clcl - t clcx 22 - ns t clcx low time see figure 13 22 t clcl - t chcx 22 - ns t clch rise time see figure 13 -5 -5ns t chcl fall time see figure 13 -5 -5ns shift register (uart mode 0) t xlxl serial port clock cycle time 16 t clcl - 888 - ns t qvxh output data set-up to clock rising edge 13 t clcl - 722 - ns t xhqx output data hold after clock rising edge -t clcl + 20 - 75 ns t xhdx input data hold after clock rising edge - 0 - 0 ns t dvxh input data valid to clock rising edge 150 - 150 - ns
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 40 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 12. shift register mode timing. 0 1234567 valid valid valid valid valid valid valid valid t xlxl 002aaa425 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 13. external clock timing. t chcl t clcx t chcx t c t clch 002aaa416 0.2 v dd + 0.9 0.2 v dd - 0.1 v v dd - 0.5 v 0.45 v table 11: ac characteristics, isp entry mode v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ max unit t vr rst delay from v dd active 50 - - m s t rh rst high time 1 - 32 m s t rl rst low time 1 - - m s fig 14. isp entry waveform. 002aaa426 v dd rst t rl t vr t rh
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 41 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. comparator electrical characteristics [1] this parameter is characterized, but not tested in production. table 12: comparator electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise speci?ed. t amb = - 40 cto+85 c for industrial, unless otherwise speci?ed. symbol parameter conditions min typ max unit v io offset voltage comparator inputs - - 20 mv v cr common mode range comparator inputs 0 - v dd - 0.3 v cmrr common mode rejection ratio [1] -- - 50 db response time - 250 500 ns comparator enable to output valid - - 10 m s i il input leakage current, comparator 0 < v in philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 42 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. package outline fig 15. tssop20 (sot360-1). unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 43 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. fig 16. dip20 (sot146-1). unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot146-1 99-12-27 03-02-13 a min. a max. b z max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2 4.2 0.51 3.2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.078 0.17 0.02 0.13 sc-603 ms-001 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 20 1 11 10 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) (1) dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core product data rev. 08 15 december 2004 44 of 46 9397 750 14469 ? koninklijke philips electronics n.v. 2004. all rights reserved. 14. revision history table 13: revision history rev date cpcn description 08 20041215 - product data (9397 750 14469) modi?cation: ? added 18 mhz information. 07 20041203 - product data (9397 750 14251) 06 20031121 - product data (9397 750 12285); ecn 853-2403 01-a14557 of 18 november 2003 05 20031007 - product data (9397 750 12121); ecn 853-2403 30391 of 30 september 2003 04 20030909 - product data (9397 750 11945); ecn 853-2403 30305 of 5 september 2003 03 20030811 - preliminary data (9397 750 11786) 02 20030522 - objective data (9397 750 11532) 01 20030505 - preliminary data (9397 750 11387)
9397 750 14469 philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 08 15 december 2004 45 of 46 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. 18. licenses level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c speci?cation de?ned by philips. this speci?cation can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 15 december 2004 document order number: 9397 750 14469 contents philips semiconductors p89lpc920/921/922/9221 8-bit microcontrollers with two-clock 80c51 core 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 principal features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 special function registers. . . . . . . . . . . . . . . . . . . . . . 9 8 functional description . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2.1 clock de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2.2 cpu clock (oscclk) . . . . . . . . . . . . . . . . . . . . . . . 14 8.2.3 low speed oscillator option . . . . . . . . . . . . . . . . . . . 14 8.2.4 medium speed oscillator option . . . . . . . . . . . . . . . . 14 8.2.5 high speed oscillator option . . . . . . . . . . . . . . . . . . . 14 8.2.6 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.3 on-chip rc oscillator option . . . . . . . . . . . . . . . . . . 15 8.4 watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 15 8.5 external clock input option . . . . . . . . . . . . . . . . . . . . 15 8.6 cpu clock (cclk) wake-up delay. . . . . . . . . . . . . . 17 8.7 cpu clock (cclk) modi?cation: divm register . . . 17 8.8 low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.9 memory organization . . . . . . . . . . . . . . . . . . . . . . . . 17 8.10 data ram arrangement . . . . . . . . . . . . . . . . . . . . . . 18 8.11 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.11.1 external interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 18 8.12 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.12.1 port con?gurations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.12.2 quasi-bidirectional output con?guration. . . . . . . . . . 20 8.12.3 open-drain output con?guration. . . . . . . . . . . . . . . . 20 8.12.4 input-only con?guration . . . . . . . . . . . . . . . . . . . . . . 20 8.12.5 push-pull output con?guration . . . . . . . . . . . . . . . . . 20 8.12.6 port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 20 8.12.7 additional port features . . . . . . . . . . . . . . . . . . . . . . 21 8.13 power monitoring functions . . . . . . . . . . . . . . . . . . . 21 8.13.1 brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.13.2 power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14 power reduction modes . . . . . . . . . . . . . . . . . . . . . . 21 8.14.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.14.2 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.14.3 total power-down mode . . . . . . . . . . . . . . . . . . . . . . 22 8.15 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.15.1 reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.16 timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 23 8.16.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.16.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.16.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.16.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.16.5 mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.16.6 timer over?ow toggle output. . . . . . . . . . . . . . . . . . . 24 8.17 real-time clock/system timer. . . . . . . . . . . . . . . . . . 24 8.18 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.18.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.18.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.18.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.18.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.18.5 baud rate generator and selection . . . . . . . . . . . . . . 25 8.18.6 framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.18.7 break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.18.8 double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.18.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 26 8.18.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.19 i 2 c-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 27 8.20 analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.20.1 internal reference voltage . . . . . . . . . . . . . . . . . . . . . 29 8.20.2 comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 30 8.20.3 comparators and power reduction modes . . . . . . . . 30 8.21 keypad interrupt (kbi) . . . . . . . . . . . . . . . . . . . . . . . 30 8.22 watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.23 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.23.1 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.23.2 dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.24 flash program memory. . . . . . . . . . . . . . . . . . . . . . . 32 8.24.1 general description. . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.24.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.24.3 isp and iap capabilities of the p89lpc920/921/922/9221 . . . . . . . . . . . . . . . . 32 8.25 user con?guration bytes . . . . . . . . . . . . . . . . . . . . . . 34 8.26 user sector security bytes . . . . . . . . . . . . . . . . . . . . 34 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 38 12 comparator electrical characteristics . . . . . . . . . . . 41 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 16 de?nitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 18 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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